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Ordering number : EN5159A
CMOS LSI
LC74772V
Camcorder On-Screen Display LSI
Overview
The LC74772V is a CMOS LSI that implements on-screen display for camcorders. It displays characters and patterns in a camcorder viewfinder under microprocessor control. The LC74772V displays a 12 x 18 dot font with 256 characters.
Package Dimensions
unit: mm 3175A-SSOP24
[LC74772V]
Features
* Screen format: 12 lines 24 characters (up to 288 characters) * Number of characters displayed: Up to 288 characters * Character format: 12 (horizontal) x 18 (vertical) dots * Number of characters in font: 256 characters * Character sizes: Normal and double, specified in line units * Display start position -- Horizontal: 64 positions -- Vertical: 64 positions * Character reverse video function: Individual characters can be displayed in reverse video. * Types of blinking: Two types with periods of 1.0 and 0.5 seconds, specifiable on a per character basis. (Blinking has a 60% display on duty.) (Four divisors: 1/25, 1/30, 1/50, 1/60) * Outputs: R, G, B plus 2 output systems Or: 4 output systems (character data and blanking data: 4 outputs each) * External control input: 8-bit serial data input format
SANYO: SSOP24
Specifications
Absolute Maximum Ratings
Parameter Supply voltage Input voltage Output voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD VIN VOUT Pd max Topr Tstg VDD All input pins CKOUT, CHA4, BLK4, CHA3, BLK3, B, G, R, BLANK Ta = 25C Conditions Ratings VSS - 0.3 to VSS + 7.0 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to VDD + 0.3 300 -30 to +70 -40 to +125 Unit V V V mW C C
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O3096HA(OT)/D3095HA (OT) No. 5159-1/16
LC74772V Allowable Operating Ranges at Ta = -30 to +70C
Parameter Supply voltage Input high-level voltage Input low-level voltage Oscillator frequency Symbol VDD VIH VIL FOSC VDD CTRL1, TESTIN, CS, SCLK, SIN, OUTMOD, HSYNC, VSYNC, RST CTRL1, TESTIN, CS, SCLK, SIN, OUTMOD, HSYNC, VSYNC, RST OSCIN, OSCOUT (LC oscillator) Conditions Ratings min 2.7 0.8 VDD VSS - 0.3 6 (8) typ 5.0 max 5.5 VDD + 0.3 0.2 VDD 10 Unit V V V MHz
Electrical Characteristics at Ta = -30 to +70C, unless otherwise specified VDD = 5 V
Parameter Symbol Conditions CKOUT, CHA4, BLK4, CHA3, BLK3, B, G, R, BLANK: VDD = 5.5 to 4.5 V (VDD = 4.4 to 2.7 V), IOH = -1.0 mA (-0.5 mA) CKOUT, CHA4, BLK4, CHA3, BLK3, B, G, R, BLANK: VDD = 5.5 to 4.5 V (VDD = 4.4 to 2.7 V), IOL = 1.0 mA (0.5 mA) CTRL1, TESTIN, CS, SCLK, SIN, OUTMOD, HSYNC, VSYNC: VIN = VDD CTRL1, TESTIN, HSYNC, VSYNC: VIN = VSS VDD pin; all outputs open, LC oscillator: 8 MHz -1 10 Ratings min 0.9 VDD typ max Unit
Output high-level voltage
VOH
V
Output low-level voltage
VOL
0.1 VDD
V
Input current Operating current drain
IIH IIL IDD
1
A A mA
Timing Characteristics at Ta = -30 to +70C, VDD = 5 0.5 V
Parameter Symbol tW (SCLK) tW (CS) tSU (CS) tSU (SIN) th (CS) th (SIN) tword twt SCLK CS (the period that CS is high) CS SIN CS SIN The time to write 8 bits of data The RAM data write time Conditions Ratings min 200 1 200 200 2 200 4.2 1 typ max Unit ns s ns ns s ns s s
Minimum input pulse width
Data setup time
Data hold time
One-word write time
No. 5159-2/16
LC74772V Serial Data Input Timing
Pin Assignment The signal names in parentheses indicate the output pin functions when 4-system output mode is used.
No. 5159-3/16
LC74772V Pin Functions
PinNo. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Symbol VSS OSCIN OSCOUT CTRL1 TESTIN CS SCLK SIN CKOUT BLK4 CHA4 NC NC BLK3 CHA3 BLANK R G B OUTMOD VSYNC HSYNC RST VDD Ground LC oscillator Clock input control Test control input Enable input Clock input Data input Clock output Blanking signal output Character data output Unused Unused Blanking signal output Character data output Blanking signal output Character data output Character data output Character data output Output control input Vertical synchronizing signal input Horizontal synchronizing Reset input Power supply Function Ground connection Connections for the coil and capacitor that form the oscillator that generates the character output horizontal dot clock. Control input that switches between LC oscillator mode and clock input mode Low: LC oscillator mode, high: clock input mode Test mode control input (The IC operates in test mode when this input is high.) Serial data input enable input Low: active (This input has hysteresis characteristics.) Serial data input clock input (This input has hysteresis characteristics.) Serial data input (This input has hysteresis characteristics.) LC oscillator clock monitor output This signal is output when RST is low. Blanking signal output (system 2) Functions as the system 4 blanking data signal output in 4-system mode. Character data signal output (system 2) Functions as the system 4 character data signal output in 4-system mode. Must be left open or tied to ground in normal operation. Must be left open or tied to ground in normal operation. Blanking signal output (system 1) Functions as the system 3 blanking data signal output in 4-system mode. Character data signal output (system 1) Functions as the system 3 character data signal output in 4-system mode. Blanking signal output (blanking signal for RGB output) Functions as the system 2 blanking data signal output in 4-system mode. Character data (R) signal output Functions as the system 2 character data signal output in 4-system mode. Character data (G) signal output Functions as the system 1 blanking data signal output in 4-system mode. Character data (B) signal output Functions as the system 1 character data signal output in 4-system mode. Control input that switches between RGB output and 4-system output Low: RGB output, high 4-system output Vertical synchronizing signal input (This input has hysteresis characteristics.) Horizontal synchronizing signal input (This input has hysteresis characteristics.) signal input System reset signal input (This input has hysteresis characteristics.) Power supply connection (+5 V) Description
Note: 1. Built-in pull-up resistors can be specified for inclusion in the CS (pin 6), SCLK (pin 7), SIN (pin 8), and RST (pin 23) pins as mask options. 2. In clock input mode (when CTRL1 is high), the function that holds the OSCIN (pin 2) pin high during an oscillator reset is stopped.
No. 5159-4/16
LC74772V Block Diagram
No. 5159-5/16
LC74772V Display Control Commands The display control commands have an 8-bit serial input format. Data is input LSB first. Display Control Command Table
First byte Command D7 COMMAND 0 System setup 1 COMMAND 1 System setup 2 COMMAND 2 Input control setup COMMAND 3 General-purpose port control COMMAND 4 Display operation control: reverse video and blinking COMMAND 5 Display control: on/off settings for each output COMMAND 6 Output control: systems 3 and 4 COMMAND 8 Display control: border COMMAND 9 Display start position COMMAND 10 Display line control COMMAND 11 RAM write address COMMAND 14 Display RAM setup data 0 0 0 0 Command code D6 0 0 0 0 D5 0 0 1 1 D4 0 1 0 1 D3 RST SYS D2 RAM CLR Data D1 OSC STP D0 TST MOD D7 -- -- -- -- D6 -- -- -- -- D5 -- -- -- -- Second byte Data D4 -- -- -- -- D3 -- -- -- -- D2 -- -- -- -- D1 -- -- -- -- D0 -- -- -- --
CSYN CLK CLK CLK MOD POLT MOD1 MOD0 VSYN HSYN DATA ART POLT POLT FMT FMT PORT OUT SET P11 RVS ON DSP 4 BLK ON DSP 3 OUT P10 BLK 1 DSP 2 DSP GSG BKC G VP3 LNF OT3 OUT P9 BLK 0 DSP 1 DSP BSG
0
1
0
0
--
--
--
--
--
--
--
--
0
1
0
1
--
--
--
--
--
--
--
--
0 1 1 1 1 1
1 0 0 0 0 1
1 0 0 1 1 1
0 0 1 0 1 BLK
DSPF DSP SL34 RSG 0 VP5 LNF SZ BKC R VP4 LNF OT4
--
--
--
--
--
--
--
--
BKC BKO4 BKO4 BKO3 BKO3 BKO2 BKO2 BKO1 BKO1 B F1 F0 F1 F0 F1 F0 F1 F0 VP2 LN SEL VP1 0 0 C7 VP0 0 0 C6 HP5 LIN 126 0 C5 HP4 LIN 115 HP3 LIN 104 HP2 LIN 93 HP1 LIN 82 HP0 LIN 71
VADR VADR VADR VADR 3 2 1 0 RV R G B
HADR HADR HADR HADR HADR 4 3 2 1 0 C4 C3 C2 C1 C0
x x Command code: (These 4 bits in the first byte identify the command.)
Command 14 is recognized by the upper 3 bits.
y
y Command data: (These bits specify the data for each command.)
* For commands 0 through 7, 8 bits of data are read in. * For commands 8 through 14, 16 bits of data are read in. * If the command 1 data-9 bit (DATAFMT) was set to 1, after the first byte of a command 14 is read in, the system goes to continuous transfer mode for reading in a series of following bytes.
Note: 1. If the CS pin is set high, the command state is set to the command 0 (system control setup) state. 2. If a system reset is executed from the RST pin or by a command reset, the command register is set tot 0.
No. 5159-6/16
LC74772V
x COMMAND 0 (System control setup 1)
First byte
Register content DA0 to DA7 7 6 5 4 3 Register name -- -- -- -- RST SYS RAM CLR OSC STP TST MOD State 0 0 0 0 0 1 0 1 0 1 0 1 Normal operation System reset Normal operation If CS is low, the reset is executed, but if CS is high this command will be excluded. Command 0 identification code Function Note
2
The VRAM clear operation is not executed when the oscillator Normal operation VRAM clear (All data is set to FE (hexadecimal)) is stopped. The LC oscillator operating state is maintained. The LC oscillator is stopped. Normal operation Test mode Valid when the display is off. VRAM write is not possible when the oscillator is stopped. Illegal setting. This bit must always be set to 0.
1
0
Note: This register is set to 0 on a reset (either by the RST pin or by a command reset).
Notes on command settings 1. RSTSYS: A command reset is executed immediately after the data is read. The reset is cleared by returning the CS pin to high to reset this register. The reset is also cleared if this command is executed consecutively or if this register is set to 0. 2. RAMCLR: The RAM can only be erased when display is off. This operation is not executed during display. This operation cannot be executed if the LC oscillator is stopped. Only use this command when the LC oscillator is operating. * This command bit is automatically cleared when the RAM erase operation completes. * Once the RAM erase command has been read in, the following time is required to complete the operation. -- Tclear = 5 [s] + 4/fOSC (LC-oscillator) x 288 3. OSCSTP: The LC oscillator stop command stops the LC oscillator connected to pins 2 and 3 (OSCIN and OSCOUT). The oscillator stop command is only executed when display is off. It is not executed if display is in progress. * In external clock input mode, this command stops the acquisition of that clock signal. 4. TSTMOD: The test mode command is executed if the TESTIN pin (pin 5) is high. This command should not be used by applications in normal operation.
No. 5159-7/16
LC74772V
y COMMAND 1 (System control setup 2)
First byte
Register content DA0 to DA7 7 6 5 4 Register name -- -- -- -- CSYN MOD State 0 0 0 1 0 1 CLK POLT 0 1 0 1 0 1 HSYNC (pin 22) functions as the horizontal synchronizing signal input HSYNC (pin 22) functions as the composite synchronizing signal input The system clock has a positive polarity. The system clock has a negative polarity. MOD1 0 0 0 CLK MOD0 1 1 MOD0 0 1 0 1 Operation LC oscillator mode Clock input (1 dot) Clock input (NTSC) Clock input (PAL) Valid when the CTRL1 pin (pin 4) is high. The input clock frequency in clock input mode is either 4fsc or the dot clock frequency. The VSYNC pin (pin 21) must be tied to ground or VDD in composite synchronizing signal input mode. This sets the clock polarity for system operation when pin 2 is used as a clock input. Command 1 identification code Function Note
3
2
1
CLK MOD1
z COMMAND 2 (Input control)
First byte
Register content DA0 to DA7 7 6 5 4 3 Register name -- -- -- -- VSYN POLT HSYN POLT State 0 0 1 0 0 1 0 1 0 1 0 ATR FMT 0 1 The vertical synchronizing signal input polarity is low active. The vertical synchronizing signal input polarity is high active. The horizontal synchronizing signal input polarity is low active. The horizontal synchronizing signal input polarity is high active. Data is transferred in 16-bit units. Continuous transfers with the upper 8 bits input first and then the lower 8 bits RV specifies the reverse video display function. RV specifies system 3 output control. Sets the pin 21 (VSYNC) signal input polarity. Sets the pin 22 (HSYNC) signal input polarity. Command 2 identification code Function Note
2
1
DATA FMT
Sets the COMMAND 14 data transfer format.
COMMAND-14 Data 11: Valid in RV RGB output mode.
Note: This register is set to 0 on a reset (either by the RST pin or by a command reset).
No. 5159-8/16
LC74772V
{ COMMAND 3 (General-purpose port control)
First byte
Register content DA0 to DA7 7 6 5 4 3 Register name -- -- -- -- PORT SET OUT P11 OUT P10 OUT P9 State 0 0 1 1 0 1 0 1 0 1 0 1 System 4 functions as a normal character and border outputs. System 4 functions as general-purpose ports. The pin 11 output is set to low. The pin 11 output is set to high. The pin 10 output is set to low. The pin 10 output is set to high. The pin 9 output is set to low. The pin 9 output is set to high. Controls the pin 10 (BLK4) and pin 11 (CHA4) outputs. Sets the output when PORTSET is set to 1. Sets the output when PORTSET is set to 1. Sets the output for pin 9 during normal operation (other than during a reset). Command 3 identification code Function Note
2
1
0
| COMMAND 4 (Display control: reverse video and blinking)
First byte
Register content DA0 to DA7 7 6 5 4 Register name -- -- -- -- RVS ON State 0 1 0 0 0 1 0 1 0 1 BLK1 1 0 0 BLK0 1 BLK1 0 0 1 1 BLK0 0 1 0 1 Operation V x 25 (PAL: 0.5 s) V x 30 (NTSC: 0.5 s) V x 50 (PAL: 1.0 s) V x 60 (NTSC: 1.0 s) The blinking period setting The duty is 60% for all types. Character display on: 60% Character display off: 40% V: Vertical period -- Characters for which the attribute is specified are displayed in reverse video. -- Characters for which the attribute is specified are displayed blinking. Command 4 identification code Function Note
3
2
BLK ON
Note: This register is set to 0 on a reset (either by the RST pin or by a command reset).
No. 5159-9/16
LC74772V
} COMMAND 5 (Display control: on/off settings for each output system)
First byte
Register content DA0 to DA7 7 6 5 4 3 Register name -- -- -- -- DSP4 State 0 1 0 1 0 1 0 1 0 1 DSP2 1 0 0 DSP1 1 System 1 (RGB) output on System 2 output on System 1 (RGB) output off System 4 output off System 4 output on System 3 output off System 3 output on System 2 output off Pin 10 (BLK4) and pin 11 (CHA4) output control Pin 14 (BLK3) and pin 15 (CHA3) output control Pin 16 (BLK2) and pin 17 (CHA2) output control Invalid in RGB output mode. Pin 18 (BLK1) and pin 19 (CHA1) output control Functions as the RGB output control in RGB output mode. Command 5 identification code Function Note
2
DSP3
~ COMMAND 6 (Output control: systems 3 and 4 output control settings)
First byte
Register content DA0 to DA7 7 6 5 4 Register name -- -- -- -- DSPF SL34 State 0 1 1 0 0 1 0 1 0 1 0 1 Sets the system 3 output conditions according to the command described below. Sets the system 4 output conditions according to the command described below. DSPRSG DSPGSG DSPBSG 0 0 1 DSP GSG 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Output selection Signals other than R, G, B are output. B is output. G is output. G and B are output. R is output. R and B are output. R and G are output. All of R, G, B are output. Note: The following registers are set to 1 during a reset. DSPRSG DSPGSG DSPBSG As a result, the "All of R, G, B are output" state is selected during a reset. Only system 4 is valid in 4-system output mode. System 4 cannot be set when the general-purpose output port usage is specified. Command 6 identification code Function Note
3
2
DSP RSG
0
DSP BSG
Note: This register is set to 0 on a reset (either by the RST pin or by a command reset).
No. 5159-10/16
LC74772V
COMMAND 8 (Output control: background color setting: RGB output mode)
First byte
Register content DA0 to DA7 7 6 5 4 3 Register name -- -- -- -- State 1 0 0 0 0 0 2 BKCR 1 0 1 BKCG 1 0 0 BKCB 1 -- BKCR 0 0 0 0 1 1 1 1 BKCG 0 0 1 1 0 0 1 1 BKCB 0 1 0 1 0 1 0 1 Background color Black Blue Green Cyan Red Magenta Yellow White Background color setting in RGB output mode This command is invalid in 4-system output mode. * Invalid when pin 20 (OUTMOD) is high. * Valid when pin 20 (OUTMOD) is low. Command 8 identification code Function Note
Second byte
Register content DA0 to DA7 Register name State 0 BKO4F1 BKO4F0 1 0 1 0 BKO3F1 BKO3F0 1 0 1 0 BKO2F1 BKO2F0 1 0 1 0 BKO1F1 BKO1F0 1 0 1 Note: This register is set to 0 on a reset (either by the RST pin or by a command reset). 0 0 0 BKO1 F0 1 1 0 1 0 1 Operation function No background or border Font size Border Areas other than the font (all filled) The system 1 or RGB output border setting 0 0 2 BKO2 F0 1 1 0 1 0 1 Operation function No background or border Font size (black characters) Border Areas other than the font (all filled) The system 2 output border setting This command is invalid in RGB output mode. * Invalid when pin 20 (OUTMOD) is low. * Valid when pin 20 (OUTMOD) is high. 0 0 4 BKO3 F0 1 1 0 1 0 1 Operation function No background or border Font size (black characters) Border Areas other than the font (all filled) The system 3 output border setting 0 0 6 BKO4 F0 1 1 0 1 0 1 Operation function No background or border Font size (black characters) Border Areas other than the font (all filled) The system 4 output border setting Function Note
7
BKO4 F1
5
BKO3 F1
3
BKO2 F1
1
BKO1 F1
No. 5159-11/16
LC74772V
COMMAND 9 (Display start position setting)
First byte
Register content DA0 to DA7 7 6 5 4 Register name -- -- -- -- State 1 0 0 1 0 3 VP5 1 Where H is horizontal period pulse period. 0 2 VP4 1 0 1 VP3 1 0 0 VP2 1 If VS is the vertical display start position then: VS = H x ( 2nVPn) + 16H
n=0 5
Function
Note
Command 9 identification code
Second byte
Register content DA0 to DA7 7 Register name VP1 State 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 If VS is the horizontal display start position then: HS = Tc x ( 2nHPn) + 12Tc
n=0 5
Function
Note
6
VP0
5
HP5
4
HP4
3
HP3
Where Tc is a single period of the LC oscillator connected to pins 2 and 3 (OSCIN and OSCOUT), or: Tc is the period of the input clock (4fsc input) if CTRL1 (pin 4) is high. NTSC mode: 7.159 MHz = 4fsc x 1/2 PAL mode: 7.094 MHz = 4fsc x 2/5
2
HP2
1
HP1
0
HP0
Note: This register is set to 0 on a reset (either by the RST pin or by a command reset).
No. 5159-12/16
LC74772V
COMMAND 10 (Display line control)
First byte
Register content DA0 to DA7 7 6 5 4 3 Register name -- -- -- -- LNF SZ LNF OT4 LNF OT3 LNF SEL State 1 0 1 0 0 1 0 1 0 1 0 1 -- Sets the character size. -- Sets the system 4 display line. -- Sets the system 3 display line. The line specified by the next 6 bits is one of lines 1 to 6. The line specified by the next 6 bits is one of lines 7 to 12. Controls the line switching specified by the six bits in the second byte. Invalid in system 4 output setup mode. Invalid in general-purpose port mode. Command 10 identification code Function Note
2
1
0
Second byte
Register content DA0 to DA7 7 6 5 Register name -- -- LIN 126 LIN 115 LIN 104 LIN 93 LIN 82 LIN 71 State 0 0 0 1 0 1 0 1 0 1 0 1 0 1 -- -- Clears the line 6 (12) setting. Sets line 6 (12). Clears the line 5 (11) setting. Sets line 5 (11). Clears the line 4 (10) setting. Sets line 4 (10). Clears the line 3 (9) setting. Sets line 3 (9). Clears the line 2 (8) setting. Sets line 2 (8). Clears the line 1 (7) setting. Sets line 1 (7). The character size or display line setting 0: Character size specification = normal Display line specification = off 1: Character size specification = double size Display line specification = on Function Note
4
3
2
1
0
Note: This register is set to 0 on a reset (either by the RST pin or by a command reset).
No. 5159-13/16
LC74772V
11
COMMAND 11 (Display RAM write address setting)
First byte
Register content DA0 to DA7 7 6 5 4 3 Register name -- -- -- -- VADR 3 VADR 2 VADR 1 VADR 0 State 1 0 1 1 0 1 0 1 0 1 0 1 The range of the display RAM vertical address (line address) setting is from 0 to B (hexadecimal) (12 lines). Values of C (hexadecimal) or larger are not allowed. Command 11 identification code Function Note
2
1
0
Second byte
Register content DA0 to DA7 7 6 5 4 Register name -- -- -- HADR 4 HADR 3 HADR 2 HADR 1 HADR 0 State 0 0 0 0 1 0 1 0 1 0 1 0 1 The range of the display RAM horizontal address (character address) setting is from 00 to 17 (hexadecimal) (24 characters). Values of 18 (hexadecimal) or larger are not allowed. -- -- -- Function Note
3
2
1
0
Note: This register is set to 0 on a reset (either by the RST pin or by a command reset).
No. 5159-14/16
LC74772V
12
COMMAND 14 (Display RAM setup data)
First byte
Register content DA0 to DA7 7 6 5 4 Register name -- -- -- BLK State 1 1 1 0 1 0 1 0 1 0 1 0 1 -- Blinking character specification -- Reverse video character specification -- R output specification (system 3 output in 4-system output mode) -- G output specification (system 2 output in 4-system output mode) -- B output specification (system 1 output in 4-system output mode) Command 14 identification code Function Note
3
RV
2
R
1
G
0
B
Second byte
Register content DA0 to DA7 7 Register name C7 State 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Character code setting There are 256 characters (00 to FF hexadecimal). FE hexadecimal is handled as blank data. Nothing is displayed, whatever the other conditions are set to. FF hexadecimal functions as the transfer termination code for character-code-only continuous transfers. Continuous transfer mode is set up by setting the data 0 bit (DATAFMT) in COMMAND 2 to 1. Function Note
6
C6
5
C5
4
C4
3
C3
2
C2
1
C1
0
C0
Note: This register is set to 0 on a reset (either by the RST pin or by a command reset).
No. 5159-15/16
LC74772V Display Screen Organization The display screen consists of 12 lines of 24 characters each. Thus the maximum number of characters that can be displayed is 288 characters. The display memory address consists of a line address (VADR0, VADR1, VADR2, and VADR3 representing values from 0 to B (hexadecimal)), and a column (character position) address (HADR0, HADR1, HADR2, HADR3, and HADR4 representing values from 0 to 17 (hexadecimal)). Display Screen Organization (Display memory address)
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of August, 1997. Specifications and information herein are subject to change without notice. No. 5159-16/16

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